Hello.
I have a pulse train of events in time saved to an ASCII file.
I wish to use Verilog or Verilog-A to produce a block that will give a logical '1' when the simulator time matches values in the ASCII file.
My ASCII file looks like this:
5.062e-06
8.687e-06
1.376e-05
1.649e-05
2.190e-05
2.195e-05
3.462e-05
5.112e-05 (... etc)

I have the following code but get syntax errors on lines I'm sure are right (as per the 2008 version of the Verilog manual):

module Matlab_Ctrl_In(Vp);
     output Vp;                  
     voltage Vp;

     parameter string FILEPATH = "/home/s0458323/matlab/SPAD_Comms_Models_2/FullSystemSimData/ToCadence/";
     parameter string FILENAME = "ArrivalTrainOutMAT_tT_100_14-05-2010_123609.txt";
     parameter real ModFreq = 1e2;
     parameter real SampleRatio = 100;
     parameter real Fs = ModFreq*SampleRatio*2;
     parameter real DeltaT = 1/Fs;                  
     parameter string T_pulse = "0.000";            
     integer fd;                              
     real code = 0;                  
     fd = $fopen({FILEPATH,FILENAME}, "r");

analog begin

code = %gets(T_pulse,fd)
T_now = $abstime;

@(timer(T_now, T_step))
begin
     if (T_pulse >= T_now && T_pulse <= T_now+T_step)
     begin
           V(Vp) <+ 1;
     end
end
end
endmodule

The code is to be used with a model of a diode that breaks down at specific times, as controlled by a MATLAB model that simulates Poisson inter-arrival times, and various other effects.
It should be a simple matter of reading the next line of the ASCII file and checking to see if it has occurred, along with a fast repetition rate to ensure all events are timed correctly.

Any help would be a massive massive help.
Ed Fisher

Setting the T_now to $abstime and then using T_now immediately in a timer event is not helping either: the timer event will trigger at each time step, and most likely the T_now gets updated before the first T_step is ever reached. This is not a syntax error, however, it just makes your code behave badly or not at all...

The line with code = %gets() also misses a semicolon at the end.

Marq

Just another try: assuming the data in the file are strictly monotonous the following code will read each line in order and not start reading the next line until the current line has been matched. It assumes that the time values in the data file are all at least T_step apart.

Code:

module Matlab_Ctrl_In(Vp);
  output Vp;
  voltage Vp;

  parameter string FILEPATH = "/home/s0458323/matlab/SPAD_Comms_Models_2/FullSystemSimData/ToCadence/ArrivalTrainOutMAT_tT_100_14-05-2010_123609.txt";
  parameter real ModFreq = 1e2;
  parameter real SampleRatio = 100;
  parameter real Fs = ModFreq*SampleRatio*2;
  parameter real DeltaT = 1/Fs;
  parameter string T_pulse = "0.000";

  integer fd, out;
  real code;

  analog begin
    @(initial_step)
	fd = $fopen(FILEPATH, "r");

    if (code == 0)
	code = fscanf(fd, "%g", T_pulse);

    T_now = $abstime;
    out = (T_pulse >= T_now && T_pulse <= T_now+T_step);
    if (out == 1)
	code = 0;

    V(Vp) <+ out;

  end

endmodule 

Marq

Ok so first things first. I have changed the MATLAB to output hex values to make getting the data into verilog easier. First I need a string parameter set to a default value, that can be changed from the cds window like a parameter real vdd etc.


module Matlab_Ctrl_In(Vp);
     output Vp;                  
     voltage Vp;

     parameter real VDD = 1.2;

     parameter string default_name = "John Smith";

endmodule            

This gives a syntax error for the string but this is actually directly taken from the manual. Any help before i move onto getting hex data to memory      . Thanks.      

I just don't get verilog-a. Just put the above in and compiled it, the line parameter string FILEPATH, gives me an error straight away.
Why would it do that, is it the compiler? Cadence is using SpectreHDL compiler.

I've used verilog-a before but not file i/o, strings or time based events.
Cheers.
Ed

Looks like version 5.10.41.

Thanks for your help, if the department doesn't support it, there isn't much I can do.
Thanks.
Ed