e.fisher
New Member
Offline
Posts: 6
Edinburgh
|
Hello. I have a pulse train of events in time saved to an ASCII file. I wish to use Verilog or Verilog-A to produce a block that will give a logical '1' when the simulator time matches values in the ASCII file. My ASCII file looks like this: 5.062e-06 8.687e-06 1.376e-05 1.649e-05 2.190e-05 2.195e-05 3.462e-05 5.112e-05 (... etc)
I have the following code but get syntax errors on lines I'm sure are right (as per the 2008 version of the Verilog manual):
module Matlab_Ctrl_In(Vp); output Vp; voltage Vp;
parameter string FILEPATH = "/home/s0458323/matlab/SPAD_Comms_Models_2/FullSystemSimData/ToCadence/"; parameter string FILENAME = "ArrivalTrainOutMAT_tT_100_14-05-2010_123609.txt"; parameter real ModFreq = 1e2; parameter real SampleRatio = 100; parameter real Fs = ModFreq*SampleRatio*2; parameter real DeltaT = 1/Fs; parameter string T_pulse = "0.000"; integer fd; real code = 0; fd = $fopen({FILEPATH,FILENAME}, "r");
analog begin
code = %gets(T_pulse,fd) T_now = $abstime;
@(timer(T_now, T_step)) begin if (T_pulse >= T_now && T_pulse <= T_now+T_step) begin V(Vp) <+ 1; end end end endmodule
The code is to be used with a model of a diode that breaks down at specific times, as controlled by a MATLAB model that simulates Poisson inter-arrival times, and various other effects. It should be a simple matter of reading the next line of the ASCII file and checking to see if it has occurred, along with a fast repetition rate to ensure all events are timed correctly.
Any help would be a massive massive help. Ed Fisher
|