Hi all,
I was just wondering how often Silicon results are different from predicted in all PVT corners.  I have following line of thoughts on this.  Please comment.

1.  Sometimes even if the circuit is verified in all PVT corners but still doesn't work on Si even for an established process.  Why so ?  Is it like I-V or C-V of devices  are not modeled perfectly in some regions ? Is it because some side effects of switching of multiple transistors, substrate noise, latch up etc  are not captured in post RCX simulations?  

2.  When do we need to go for montecarlo analysis and when can we consider PVT simulations with four digital process corner sufficient to expect working Si ?

3.  What it the motivation behind keeping Si proof of the design mandatory, for research papers in good conferences?  Working of idea can be well proven  simulations itself. Then why so much of importance is given to Si proof?

-CA

When I visited a Chinese university, a PhD candidate asked a similar question: How much margin is needed that the circuit really works in reality??

They made a IR remote control IC having a 38kHz bandpass filter internally. It was a gmC filter, and they assumed to treat RC tolerances a trim range of +-50% is enough. However the chips come back with even much larger variations in center frequency. So they switched away from the Chinese foundry, but also the 2nd fab gave similar variations.

In another French design for a temp sensor the accuracy was something like +-2°C vs PVT corners, but the real devices varied by +-50°C!!

In my own 1st RF PA design the Pout was too low. I we turned on the RF, the bandgap voltage goes down by 30%, resulting in too low bias current. The reason was that the big Miller cap bottom side plate picked up the substrate noise, and was rectified internally.

Both shows that PVT analysis is by far not enough, also do this:

- Look also at mixed corners, like SF, FS or bigCsmallRslowMOS!
- Check each factor separately for best understanding
- Do MC run with process variations
- Do MC run with mismatch variations (that was missing for the both mentioned design examples!!)
- Run parasitic extraction carefully (i.e. having decoupled mode is often much too ideal). RF designs need often also L extraction.
- Include package, maybe even a little substrate model (a simple model is better than nothing)
- Combine all the worst-cases
- Plan for debugging!!!

And do not pamper your design : If you want T=-25...100°C, better do a much larger sweep and try to understand why the circuit fails in certain situations, then improve further and implement backup solutions, such as trimmings.

Bye Stephan

Totally depends on how good your model is.

Give this a read:

http://effectiveelectrons.com/whitepapers/simulationvssilicon.pdf