when I simulate verilogA xor gate (copied from desinger-guide.org), Cadence CIW shows that "wave3 is not a waveform object tat can be displayed and will be turned OFF automatically"
There is no error on the code and I could simulate other verilogA code like latch.
xor verilogA code:
Code:`include "constants.vams"
`include "disciplines.vams"
module axor (out, in1, in2);
//Copied from designers-guide.org
output out; voltage out;
input in1, in2; voltage in1, in2;
parameter real vh = 1; // output voltage in high state
parameter real vl = 0; // output voltage in low state
parameter real vth = (vh + vl)/2; // threshold voltage at inputs
parameter real td = 0 from [0:inf); // delay to start of output transition
parameter real tt = 0 from [0:inf); // transition time of output signals
analog begin
@(cross(V(in1) - vth) or cross(V(in2) - vth))
;
V(out) <+ transition( ((V(in1) > vth) ^ (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule
May I know why? I am new to verilogA.
I am using cadence 5141, mmsim61 spectreRF