kumar.g
Community Member
![* *](https://designers-guide.org/forum/Templates/Forum/default/stargold.gif) ![* *](https://designers-guide.org/forum/Templates/Forum/default/stargold.gif)
Offline
Posts: 51
Frankfurt, Germany
|
Hi all,
I am using a generate statement to instantiate a delay module (cur_starved_delay) 11 times. The basic idea is to model a 11 stage ring oscillator using current starved delay cell. But i get syntax error in generate statement. Can anyone help me with this. The code is attached below.
`include "constants.vams" `include "disciplines.vams"
module cur_starved_delay (Vin,Vbias_p,Vbias_n,Vdd,Vss, Vout);
parameter real C_load = 1e-12; parameter real Kp = 1; parameter real Kn = 1; parameter real Vt = 0.2; parameter real pos_tol = 0.2; parameter real neg_tol = -0.2;
input Vin,Vbias_p,Vbias_n,Vdd,Vss; output Vout;
voltage Vin,Vbias_p,Vbias_n,Vdd,Vss,Vout;
voltage V_swing,Vsg_p,Vgs_n; current I_p,I_n; real Td_p,Td_n,V_ph;
analog begin
V(V_swing) <+ V(Vdd) - V(Vss); V(Vsg_p) <+ V(Vdd) - V(Vbias_p); V(Vgs_n) <+ V(Vbias_n) - V(Vss); I(I_p) <+ Kp*pow((V(Vsg_p) - Vt),2); I(I_n) <+ Kn*pow((V(Vgs_n) - Vt),2);
if ((V(Vin) <= V(Vss) + pos_tol) && (V(Vin) >= V(Vss) - neg_tol)) begin Td_p = (V(V_swing)/I(I_p))*C_load; end else if ((V(Vin) <= V(Vdd) + pos_tol) && (V(Vin) >= V(Vdd) + neg_tol)) Td_n = (V(V_swing)/I(I_p))*C_load;
@(cross(V(Vin)-(V(V_swing)/2),+1)) begin V_ph = V(Vss); end @(cross(V(Vin)-(V(V_swing)/2),-1)) begin V_ph = V(Vdd); end V(Vout) <+ transition(V_ph,0,Td_p,Td_n); end
endmodule
module multiphase_vco(Vbias_p,Vbias_n,Vdd,Vss, out);
parameter integer ZERO_BIT = 0; parameter integer NO_STAGE = 11 from [3:67]; parameter real C_load = 1e-12; parameter real Kp = 1; parameter real Kn = 1; parameter real Vt = 0.2; parameter real pos_tol = 0.2; parameter real neg_tol = -0.2;
genvar i;
input Vbias_p,Vbias_n,Vdd,Vss; output [NO_STAGE-1:0] out;
voltage Vbias_p,Vbias_n,Vdd,Vss; electrical [NO_STAGE-1:0] out; electrical [NO_STAGE:0]ph_out;
generate for (i =1;i<=11;i=i+1) begin cur_starved_delay #(.C_load(C_load),.Kp(Kp),.Kn(Kn),.Vt(Vt),.pos_tol(pos_tol),.neg_tol(neg_tol)) D_i(.Vin(ph_out[i-1]),.Vbias_p(Vbias_p),.Vbias_n(Vbias_n),.Vdd(Vdd),.Vss(Vss),.Vout(ph_out[i])); end endgenerate
analog begin V(ph_out[0]) <+ V(ph_out[NO_STAGE]);
@(initial_step) begin V(ph_out[ZERO_BIT]) <+ V(Vss); end
end
endmodule
|