Hello,
I have a VerilogA model that is working well in Spectre/APS. How I'm trying to simulate the design with Cadence AMS and get an error during the elaboration stage:
Quote: B = I(<mp>)/area;
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ncelab: *E,SYERROR (...<mypath>/veriloga/verilog.vams,102|10): Port probes are not supported in modules with hierarchy.
This a cell with some RLC components instantiated and in the code I'm trying to sens the current through one terminal. In the verilogA code this line uses the following syntax:
B = I(mp,mp) / area;
I tried naming this branch explicitly, but it does not help.
Any idea how I can work around this?
Thanks a lot in advance!
Misha