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A verilogA code to measure frequency (Read 6483 times)
supermoment
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A verilogA code to measure frequency
Jul 09th, 2010, 11:15pm
 
A verilogA code to measure frequency (copied from designers-guide)

However, i got many warnings and errors.
Is it because it is a verilogAMS rather than verilogaA?
I am using Cadence 5141 mmsim61



1) like the `timescale 1ns / 1ps ->

Warning from spectre during SpectreHDL compile.
   "xxxx/freq_meas/veriloga/veriloga.va", line 6:
       Warning: `timescale directive is found in the module, if without a
       `default_transition directive or local setting of transitions in either
       transition filters or Z-transforms. In Verilog-A this results in the
       `timescale setting the transistion time which is not supported by the
       Verilog-AMS LRM.  Please use `default_transition instead to set default
       transition time for transition filters or zi_* filters.

Sound like I could I use this command.

2)
Line14 "initial begin<<--?" syntax error

Code:
[color=#0000ff]`timescale 1ns / 1ps[/color]

module freq_meas (clk);
    input clk;
    real last_time, current_time, freq;

[color=#0000ff]    initial begin[/color]
	last_time = 0.0;
	freq = 0.0;
    end
    always @(posedge clk) begin
	current_time = $realtime;
	if (last_time > 0.0)
	    freq = 1.0e9 / (current_time - last_time);
	last_time = current_time;
    end
endmodule
 






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supermoment
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Re: A verilogA code to measure frequency
Reply #1 - Jul 10th, 2010, 1:46am
 
I know the issue. It is a verilogAMS code and not the verilogA code.

I have eventually made it in verilogA to measure frequency...   Smiley
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Geoffrey_Coram
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Re: A verilogA code to measure frequency
Reply #2 - Jul 12th, 2010, 6:01am
 
Quote:
Warning from spectre during SpectreHDL compile.


Seems like you incorrectly included it in the netlist, so that Spectre thinks it is SpectreHDL, not Verilog-A nor Verilog-AMS.
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Marq Kole
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Hmmm. That's
weird...

Posts: 122
Eindhoven, The Netherlands
Re: A verilogA code to measure frequency
Reply #3 - Jul 12th, 2010, 7:40am
 
Spectre has no separate statements for including SpectreHDL or Verilog-A. The ahdl_include statement will do either.

Also with the latest version of Spectre in MMSIM you will get the above results (although none of the versions I've tested -- 5.1, 6.1, and 7.2 -- say something about SpectreHDL - they all say:
"Warning from spectre during AHDL read-in."
)

The warning may suggest that the timescale directive is supported in Spectre Verilog-A, but in reality that is not the case. However, it is a warning as Spectre is still able to continue and make a successful simulation, but not taking this directive into account.

Marq
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