Hi I was trying to compile the PLL code downloaded from
http://www.designers-guide.org/VerilogAMS/

I get compilation errors with the following msg. Can anyone confirm that the code is broken & what needs to be done to fix it.

ncvlog: *E,FNDKWD (./my_rtl/pfd.v,14|34): A SystemVerilog keyword was found where an i

dentifier was expected.

module pfd (qinc, qdec, active, ref, reset);

                                         |

ncvlog: *E,EXPRCC (./my_rtl/pfd.v,14|42): expecting a right brace ('}') [13.3.1(IEEE)]

.

   input reset, active, ref;

                          |

ncvlog: *E,FNDKWD (./my_rtl/pfd.v,16|27): A SystemVerilog keyword was found where an i

dentifier was expected.

   always @(posedge ref or posedge fr_rst) begin

                      |

ncvlog: *E,ILLPRI (./my_rtl/pfd.v,27|23): illegal expression primary [4.2(IEEE)].

   always @(posedge ref or posedge fr_rst) begin

                      |

ncvlog: *E,CBYREF (./my_rtl/pfd.v,27|23): The 'ref' formal argument direction is only

allowed within tasks and functions.

   always @(posedge ref or posedge fr_rst) begin

                         |

ncvlog: *E,FNDKWD (./my_rtl/pfd.v,27|26): A Verilog keyword was found where an identif

ier was expected.

   always @(posedge ref or posedge fr_rst) begin

                                         |

ncvlog: *E,EXPSMC (./my_rtl/pfd.v,27|42): expecting a semicolon (';') [12.3.2(IEEE)].

           if (fr_rst) q1 <= 0; else q1 <= 1;

                     |

ncvlog: *E,EXPSMC (./my_rtl/pfd.v,28|15): expecting a semicolon (';') [12.3.2(IEEE)].

           if (fr_rst) q1 <= 0; else q1 <= 1;

                           |

ncvlog: *E,EXPSMC (./my_rtl/pfd.v,28|21): expecting a semicolon (';') [12.3.2(IEEE)].

           if (fr_rst) q1 <= 0; else q1 <= 1;