Hello.
Quick query. I have an extracted net list of a semiconductor pn junction device, i.e. the net list of the extracted capacitances, bulk resistances etc. The device is DRC and LVS clean but does not include the devices behaviour.
I have a separate VerilogA electrical behavioural model of the device which takes in a generic trigger pulse and gives the correct (verified) behaviour at its anode and cathode.
Of course If I put both into schematic the block will no longer LVS as the VerilogA is essentially not there.
Instead I want to add the VerilogA model into net list, preferably with code to only simulate if in electrical simulation mode rather than LVS or DCR modes.

The VerilogA prototype is:

module GeigerModel(PLUS, MINUS, PULSE)

Thanks very much.
Ed Fisher