You know I've heard that "You just need to write it correctly" sort of thing. I've written a lot of VerilogA. I've used examples from the Cadence ahdl Lib unmodified, I've read books and taken classes. Bottom line- it more often than not is the cause of my convergence problems. I have MUCH better luck using analogLib components to model behavior.
I suppose I am still doing something wrong
Thanks for the comments! I appreciate it!
I got my table model working- did indeed see strange interpolation but when I switched to order "1" - I got what I wanted- just standard PWL.
Thanks again!