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how to flush out the buffer in verilog A? (Read 4282 times)
Irvin73
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how to flush out the buffer in verilog A?
Sep 27th, 2010, 10:19am
 
Hi,
I run relatively long transient spectre simulation with some verilog-A block which on each "cycle" of simulation should print data to the log file. Like in following example -

Code:
@(cross(V(CNT_RST)-vth, +1)) begin
           // ... some code here
	   $fwrite(logFile,"%d\t%.2f\t%.2f\t%.2f\n", row_index, cds_code,reset_code,signal_code)
	  
end   



The problem is that the log file updated only after the simulation completes, and I want to do monitoring of the log during the simulation. I think there is some way to control the flushing of the buffer, can anyone help with this?

Tnanks.
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Geoffrey_Coram
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Re: how to flush out the buffer in verilog A?
Reply #1 - Sep 28th, 2010, 6:04am
 
Try
$fflush(logFile);
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Irvin73
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Re: how to flush out the buffer in verilog A?
Reply #2 - Sep 28th, 2010, 6:36am
 
It works, many thanks!

Interesting thing - this function is not documented, at least I can't find it in "Cadence®Verilog®-A Language Reference" pdf (2006). Is my documentation obsolete? Smiley

Thanks again for quick and useful response.
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Geoffrey_Coram
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Re: how to flush out the buffer in verilog A?
Reply #3 - Sep 29th, 2010, 8:45am
 
I found this in the IEEE 1800-2009 standard.

I know some vendors implement features like this in their (digital) Verilog simulators, and then I guess it's an easy port to add to their analog or AMS simulators.
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