Hi,
i'm using in my bench ideal comparator verilogA model based on Cadence ahdlLib code - the comparator voltage transfer function is modeled as hiperbolic tangent in time domain, like this:

Code:

`include "constants.vams"
`include "disciplines.vams"

module ideal_cds_cmp(vout,cmp_rst,vin_p,vin_n);
output vout;
electrical vout;
input cmp_rst;
electrical cmp_rst;
input vin_p;
electrical vin_p;
input vin_n;
electrical vin_n;


parameter real vhigh = 2.8;
parameter real vlow  = 0;
parameter real reset_value = 1;
parameter real comp_slope = 10000;
integer reset;
real vth,vreset,vout_val;


  analog begin
    
     @(initial_step) begin
         vth = (vhigh+vlow)/2 ;
         reset = 1;
         vreset = reset_value*(vhigh-vlow);
     end
  
     @(cross(V(cmp_rst)-vth, +1)) begin
           // Comparator output should be at reset value regardless of its inputs:
           reset = 1;
     end
    
     @(cross(V(cmp_rst)-vth, -1)) begin
           // Comparator output should be defined based on its inputs:
           reset = 0;
     end
    
     if (reset)
        // Reset phase:
        vout_val = vreset;
     else
        // Runinng phase:
        vout_val = vth * tanh(comp_slope*V(vin_p,vin_n)) + vth;
       
     V(vout) <+ vout_val;
  
  end // analog

endmodule

 

If I have no mistake,  comp_slope parameter should be used for DC gain modeling, but I wonder what about frequency response? The BW of such comparator seems to be unbound, isn't it?