Luke Whitaker
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Posts: 1
Marin, Switzerland
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Hello design community,
The cell I'm trying to make a verilog-ams module for has several global power nodes. There is a power on reset in the module that needs to monitor a global power signal. The top level schematic declares this node with an exclaimation point, vdd! for example. The global signal's ramp rate is controlled by a vpwl, so the global cannot be a static real value. How do I access these global power nodes from my verilog-ams module?
In general I don't like global variables (other than ground '0'), but the designer I'm working with does and wants to keep them in his design.
Thanks for your help.
Best regards,
Luke
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