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xuedashun

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tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Oct 20^th, 2010, 11:30am

I designed a 2-1 sigma-delta modulator and found fft issue I don't understand. My sim has 2 steps:
1) run "tran" analysis in spectre
2) read data from modulator output to matlab and do fft in matlab

I used 2 different sampling capacitors (200fF, 2pF) for the first integrator and other parameter (fclk, fsample, Nfft, OSR...) are all same. The fft plots show DIFFERENT noise floor (see attached picture), which I am confuse about.

I understand the modulator should have different noise performance (KT/Cs noise) with different sampling capacitor. However I used "tran" analysis in my sim and I think the "tran" analysis does NOT include the device noise. There is a "transient noise" option on my tool, but I did not use it in my sim. So the fft plots should have SAME noise floor, which is not what I see on my fft plots.

I appreciate if anyone can explain this issue.

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fft.jpg

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sheldon

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Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Reply #1 - Oct 21^st, 2010, 2:15am

Xuedashun,

� � You are trying to implement some transfer function, for example,

� � Y(z) = z^-2X(z) + (1-z^-1)^2 E(z).

Changing individual capacitors can change the transfer function.
Are the simulation results for your circuit consistent with the
results for the equivalent discrete time transfer function that you
have implemented by changing the capacitor value?

� � � � � � � � � � � � � � � � � � � � � � � � � � � Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � �Sheldon �

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xuedashun

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Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Reply #2 - Oct 21^st, 2010, 7:05am

Sheldon,

Thanks for your reply.

You are right. "Changing individual capacitors can change the transfer function."

But I changed the sampling capacitor, feedback capacitor and integration capacitor at the same time in my circuit so that the coefficients of the transfer function should keep unchanged.

The SNR value change is consistent with the sampling capacitor change (2pF->200fF). Even though this conclusion is correct, I just don't understand why it happens in this "tran" analysis. As I know, the "tran" analysis does NOT include device noise (thermal, 1/f....) so I am not supposed to see the noise floor change on the fft plots here. Do you have any other thoughts? Thank you!

Dashun

sheldon wrote on Oct 21^st, 2010, 2:15am:

Xuedashun,

� � You are trying to implement some transfer function, for example,

� � Y(z) = z^-2X(z) + (1-z^-1)^2 E(z).

Changing individual capacitors can change the transfer function.
Are the simulation results for your circuit consistent with the
results for the equivalent discrete time transfer function that you
have implemented by changing the capacitor value?

� � � � � � � � � � � � � � � � � � � � � � � � � � � Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � �Sheldon �

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sheldon

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Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Reply #3 - Oct 21^st, 2010, 9:59am

Xuedashun,

� I am just guessing, but could the design be sensitive to parasitics,
for example, op-amp input capacitance, S/D capacitances of the
switches, etc? As the device capacitance gets smaller the design
is more sensitive to the parasitics. If you try 1.0pF or 4.0pF, what
happens?

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Sheldon

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vp1953

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Posts: 172

Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Reply #4 - Oct 21^st, 2010, 6:41pm

Hi Dashun,

Could it be that your caps are somehow acting as a filter (a low pass filter) for some of the other noise sources (eg resistors, transistors etc), so that a higher cap produces a lower noise floor?

If i look at the plot, the when the cap size increased by 10x, the noise floor decreased by close to 20dB.

If the cap size increased by another 10x, - 20pf, does the noise floor go down another 20dB from that at 2pf?

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sheldon

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Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Reply #5 - Oct 21^st, 2010, 11:49pm

Xuedashun,

� See page 13 of the following reference

Course on CMOS Data Converters for Communications

A Sigma-Delta modulator design example:
From specs to measurements

Bellaterra, Barcelona (Spain) May 6-10, 2002
Fernando Medeiro, R. del R�o,
J.M. de la Rosa, B. P�rez-Verd� and �ngel Rodr�guez-V�zquez

� � � � � � � � � � � � � � � � � � � � � � � � � � � �Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � �Sheldon

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vp1953 Senior Member Offline Posts: 172	Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap Reply #6 - Oct 23^rd, 2010, 8:29am Hi Sheldon, Would it be possible for you to summarize what the issue is? Thank you in advance!
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sheldon

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Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Reply #7 - Oct 23^rd, 2010, 11:13am

Greetings,

Basically, I am invoking Occam's Razor since transient noise
analysis is not being performed, it is unlikely that the difference
is due to device noise. The example referenced shows how to
scale the capacitors in the presence of parasitics capacitance.
The simplest explanation, the explanation with the fewest
assumptions, is that the difference is due to the parasitic
capacitance in the circuit causing slight changes in the transfer
function that degrade the transfer function. Another easy test
would be replace the switches in the design with Verilog-A
switches, library bmslib cell sw_no.

Best Regards,

Sheldon

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vp1953 Senior Member Offline Posts: 172	Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap Reply #8 - Oct 24^th, 2010, 10:42am Hi Sheldon, Thank you much for your explanation and i totally agree with you. I misread the original post to think that these were the results with device noise enabled.
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HdrChopper

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Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Reply #9 - Oct 31^st, 2010, 11:54am

It might also be possible that with the scaling of the caps, although the implement the sam NTF and STF there might be dynamic range issues. My point is that by reducing the caps the internal states of the modulator can generate larger swings given a fixed input. If that swing is large enough in order to create a little bit of saturation that will show up as a larger noise floor compared to a better scaled swing at the different integartors outputs.

I would check the different outputs during the transient simulation to see wether the signal swing is not close to reference votlages for the small caps case.

Best
Tosei

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Keep it simple

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xuedashun

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Re: tran sim + fft of 2-1 sigma-delta modulator with different sampling cap
Reply #10 - Nov 9^th, 2010, 11:28am

Last month, I got some suggestions for you guys. Some people pointed out that the parasitic capacitance is possibly an issue since the sampling capacitor is very small (0.2pF and 2pF). So I used two larger sampling capacitor of the SDM21 1st stage: 1pF and 4pF in my new simulations.

The number of fft data points is 8192.

I use the tran analysis in cadence and select the "Transient Noise" option, the "Noise fmax" is set to 50*fclk. �I think this option will take the device noise into account in simulation. But the results are confusing, the 2 different sampling capacitors (1pF and 4pF) do NOT have significant difference on the fft plots, they are almost same. I expected the SNR change is larger than the result (1dB) shown on the fft plots.

Attached is the new simulation results. Could anyone give me some suggestions or explain this for me? Thank you!

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SDM21_sim.jpg

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