Hi guys,
Now, I want trace hierarchical analog value as real value.
Hierarchical Nod name is
TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc
and the SUB_A_B block is made by schematic.
I define real value as bellow in verilog ams module.
real real_value_node_abc;
real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;
but compile error occur on AMS Designer of Cadence.here is irun.err
real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;
|
ncvlog: *E,EXPLPA (aaa.vams,29|11): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;
|
ncvlog: *E,ILLHIN (aaa.vams,29|44): illegal location for a hierarchical name (TESTBENCH).
real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;
|
ncvlog: *E,EXPLPA (aaa.vams,29|52): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
module worklib.aaa:vams
errors: 3, warnings: 0
please let me know how to refer analog value as real.
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btw:
Sorry for confusing you in always my bad English.
.