Hi guys,

Now, I want trace hierarchical analog value as real value.

Hierarchical Nod name is
　TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc
and the SUB_A_B block is made by schematic.

I define real value as bellow in verilog ams module.
real real_value_node_abc;
real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;


but compile error occur on AMS Designer of Cadence.

here is irun.err

real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;
                               |
ncvlog: *E,EXPLPA (aaa.vams,29|11): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].

real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;
                                                                                                  |
ncvlog: *E,ILLHIN (aaa.vams,29|44): illegal location for a hierarchical name (TESTBENCH).

real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;
                                                   |
ncvlog: *E,EXPLPA (aaa.vams,29|52): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
       module worklib.aaa:vams
               errors: 3, warnings: 0


please let me know how to refer analog value as real.







btw:
Sorry for confusing you in always my bad English.



.

Geoffrey_Coram wrote on Nov 9^th, 2010, 5:29am:


@Geoffrey_Coram

thx for your good advice,
now i correct verilog ams code as your advice.

But after correcting , still now Error occur ( error number were reduced from 3 to 1 )

i want to check analog value of nodes of schematics base design.
here is irun.err

file: aaa.vams
real_value_node_abc = V(TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc);
                                |
ncvlog: *E,EXPLPA (aaa.vams,30|20): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
       module worklib.aaa:vams
               errors: 1, warnings: 0


even though bellow code, same error occur
electrical tempa = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc;
real_value_node_abc = V(tempa);


and proving to node which is made by verilog ams has same error too...




What does this error message means ?
i'm not sure this error comes from hierarchical node name...

plz give me some advice...
i'm waiting for your kind.

i should correct,

here is Verilog Ams code which occur error
Quote:



and here is irun.error
Quote:


when i comment out verilog ams code like this, do not occur this error.
Quote:



i wonder
1)Mr Geoffrey_Coram's comments
Quote:



2)one phrase of irun Error message
Quote:




plz give me some kind....







.

Dear kundert,

Ken Kundert wrote on Nov 11^th, 2010, 12:35am:


OK, I fully agree w/t u.

I'll try to make sample code to make same error.
DUT and TEST bench
plz wait for moment.....

Hi Sand_dolphin2,

Please sorry for my out of context question, but I need your answer very much.

So from your question I see that you are working with analog verilog or verilog ams. I am not very familiar with analog verilog, but I know pretty well the verilog digital one.

So it is not clear for me why to use analog verilog, if we have spice or other analog simulators. Could you please expand why you use the analog verilog, why spice is not acceptable for your issue. My belief is that using mixed simulations you can always model the analog part with spice and digital part with verilog.