Hi Guys,

I tried to save the variables inside a verilog-A module. A part of the verilog-A code is listed below.

Code:

`define NUM_ADC_BITS    10
   real unconverted;
   real halfref;

   real vd[0:`NUM_ADC_BITS-1];
   integer i;
 

Then I chose Outputs --> Save All... --> Select AHDL Variables (saveahdlvars) --> All. I saw unconverted, halfref, and i in the results browser. However, there was no vd. I checked the netlist, it has the following option.

Code:

saveOptions options save=allpub subcktprobelvl=3 saveahdlvars=all 

The tool versions are IC 6.1.4.500.9, and spectre sub-version  10.1.0.213.isr1.

What's wrong? Any comments are appreciated.


Thanks
Yawei

Hi Geoffrey,

Yes, it disappears if I make halfref an array, like halfref[0:1]. So I create another integer variable named dat instead of vd[0:`NUM_ADC_BITS-1]. Thanks.


Yawei