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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › Testbench in Verilog-AMS for LDO
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Testbench in Verilog-AMS for LDO (Read 2882 times)
nb439
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Testbench in Verilog-AMS for LDO
Feb 03rd, 2011, 5:20am  
Dear all,

I am trinee in Verlog-AMS modeling. I want to model a testbench in Verilog-AMS for LDO. Please help me.

Thanking you,
nanib.
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Marq Kole
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Hmmm. That's
weird...

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Eindhoven, The Netherlands
Re: Testbench in Verilog-AMS for LDO
Reply #1 - Feb 3rd, 2011, 7:54am  
I propose you start with putting some effort in the modeling. There are quite a number of helpful people around here, but we're not going to do the work for you.

Cheers,
Marq
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nb439
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Re: Testbench in Verilog-AMS for LDO
Reply #2 - Feb 4th, 2011, 12:36am  
Thank you Mr. Marq.

nanib
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