this is the verilogA code:

`include "disciplines.vams"
`include "constants.vams"

module oscillator (stby, clk_1mhz, vdd_1v8, vss);

     inout            stby, clk_1mhz, vdd_1v8, vss;
     electrical      stby, clk_1mhz, vdd_1v8, vss;

     parameter real fc   = 1e6 from (0:inf); // Frequency of the Oscillator (Hz)
     parameter real kv   = 0.0;                  // Gain (Hz/V)
   parameter real duty = 0.5 from (0:1);   // Duty Cycle.   Example: duty = 0.5
   parameter real threshold=1.0;              // vdd_1v8 must be higher than threshold for the oscillator to operate
                                         
   parameter real td=0.1n;                 // Default Delay Time for Transitions
   parameter real tr=0.1n;                 // Default Rise  Time for Transitions
   parameter real tf=0.1n;                 // Default Fall  Time for Transitions
   parameter startup_delay = 0.2u;         // Startup Delay Time for Signal clk_1mhz

   parameter real current_on=3u;           // Current Consumption when Cell is ON
   parameter real current_off=0.2u;        // Current Consumption when Cell is OFF (or not correctly biased)

   real vdd_1v8_ok, stby_ok, state, t1, icc, slope, vout_temp;

   // only for test purposes
   electrical slope_e, state_e;

   analog begin
       @(initial_step) begin
           slope = 1.0;
           state = 0.0;
           t1 = 0.0;
       end

       // Monitoring the vdd_1v8 Signal
           @(cross( V(vdd_1v8) - threshold, 0) or initial_step)
                     ;
           if (V(vdd_1v8) > threshold) vdd_1v8_ok = 1.0;   // Supply Voltage is higher than the mimimum threshold
       else                        vdd_1v8_ok = 0.0;   // Supply Voltage is lower  than the mimimum threshold
       
           // Monitoring the stby Signal
       @(cross( V(stby) - (V(vdd_1v8)/2), 0) or initial_step)
                     ;
           if (V(stby) < (V(vdd_1v8)/2))   stby_ok = 1.0 * vdd_1v8_ok;        // Oscillator is enabled
       else                            stby_ok = 0.0 * vdd_1v8_ok;        // Oscillator is disabled  

       // Monitoring the state (ON/OFF) of the oscillator
       @(cross( vdd_1v8_ok - 0.5, 0) or cross( stby_ok - 0.5, 0) or initial_step)
                     ;
       if (vdd_1v8_ok*stby_ok>0.5) begin
           state = 1.0;
       end else begin
           state = 0.0;
       end

       // Controlling the slope Signal
       @(cross( state - 0.5, +1)) begin
           t1 = $abstime;
           slope = -1.0;
       end
       if (state>0.5) begin
           @(timer(t1+startup_delay, duty/fc)) slope = -1.0 * slope;
       end else begin
           slope = slope;
       end

       // Current Consumption
       @(cross( state - 0.5, 0))
           ;
       if (state>0.5)  icc = current_on;
       else            icc = current_off;
       I(vdd_1v8, vss) <+ icc;

       vout_temp = 0.5 * (slope + 1.0) * state;

       // Output Signals
       V(clk_1mhz)     <+ vout_temp * V(vdd_1v8);
       
       // only for test purposes
       V(slope_e)      <+ slope;
       V(state_e)      <+ state;

   end

endmodule

this is the simulation result from ADE.

the slope signal reacts (goes high) when conditions are met and after the specified delay but then it goes low inmediately. It should remain high for half the period.

if you compare the results in SMASH are as expected.

How can this be?

thank you!