The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jul 17th, 2024, 4:33pm
Pages: 1
Send Topic Print
verilogA,error  when clkref & clksyn arrive at the same time (Read 7007 times)
newic
Senior Member
****
Offline



Posts: 138

verilogA,error  when clkref & clksyn arrive at the same time
Apr 23rd, 2011, 7:38am
 
`include "constants.vams"
`include "disciplines.vams"

module pi( clk0, clk90, clk180, clk270, clksyn, clkref, code0, code1, code2, code3, code ) ;

       output  clk0, clk90, clk180, clk270, code;
       input   clksyn, clkref ;
       input   code0, code1, code2, code3;

       voltage clk0, clk90, clk180, clk270, clksyn, clkref, code ;
       voltage code0, code1, code2, code3;


       parameter real vcc = 1 from (0:inf);
       //parameter real td  = 0 from [0:inf);
       //parameter real tr  = 1p from [0:inf);
       //parameter real tt  = 0  from [0:inf);
       parameter integer dir = 1  from [-1:+1] exclude 0;

       parameter real clkfreq = 6e9 from (0:inf);
       parameter real PI_step = 32;


       integer c0, c1, c2, c3;
       real    resolution;
       real    clkperiod ;
       integer validcode ;


       analog begin

               clkperiod = 1/clkfreq ;
               resolution = clkperiod/PI_step;


               @(cross(V(clksyn) - vcc/2 , dir)) begin
                       c0 = (V(code0)>vcc/2) ? 1:0;
                       c1 = (V(code1)>vcc/2) ? 1:0;
                       c2 = (V(code2)>vcc/2) ? 1:0;
                       c3 = (V(code3)>vcc/2) ? 1:0;

                       validcode = c0 + 2*c1 + 4*c2 + 8*c3 ;
               end

               V(clk0)   <+ absdelay(V(clkref), validcode*resolution);
               V(clk90)  <+ absdelay(V(clkref), validcode*resolution+clkperiod/4);
               V(clk180) <+ absdelay(V(clkref), validcode*resolution+clkperiod/2);
               V(clk270) <+ absdelay(V(clkref), validcode*resolution+3*clkperiod/4);
               V(code)   <+ validcode;
       end


endmodule


The above has no syntax error and it is able to run simulation.
However, if the input transition clkref & clksyn arrive at the same time, it produces error! How to solve this? add delay?

just tried out with other codes, it produced error Sad
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1999
Massachusetts, USA
Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #1 - Apr 25th, 2011, 5:54am
 
If you expect absdelay to respond to changes in the second argument (the delay time), I believe you need to specify a third argument for the maximum delay.
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
newic
Senior Member
****
Offline



Posts: 138

Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #2 - May 4th, 2011, 1:27am
 
it does not work as well.
please help
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1999
Massachusetts, USA
Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #3 - May 4th, 2011, 10:00am
 
newic wrote on Apr 23rd, 2011, 7:38am:

However, if the input transition clkref & clksyn arrive at the same time, it produces error!


Do you mean, the simulator generates an error message and the simulation stops?

Or it produces an erroneous result (or, at least, not the answer you expected)?
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
newic
Senior Member
****
Offline



Posts: 138

Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #4 - May 4th, 2011, 5:16pm
 
it got error when simulating. It halted at the cross function.
I tried out other method without the clksyn but replacing with clkref. it is still the same
Back to top
 
 
View Profile   IP Logged
sheldon
Community Fellow
*****
Offline



Posts: 751

Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #5 - May 4th, 2011, 9:50pm
 
newic,

 I made a few simple changes to the code and it seems to be
working correctly. Not sure what tool you are using. However,
not using a transition filter on a continuous filter is an operator
error not a tool issue.

               p0      =      absdelay(V(clkref), validcode*resolution);
                   p90      =      absdelay(V(clkref), validcode*resolution+clkperiod/4);
           p180      =      absdelay(V(clkref), validcode*resolution+clkperiod/2);
           p270      =      absdelay(V(clkref), validcode*resolution+3*clkperiod/4);

              where p0, p90, p180, and p270 are declared as integers

              V(code)   <+ transition( validcode, td, tr) ;

           V(clk0)   <+ transition( p0, td, tr, tr, tt) ;
           V(clk90)  <+ transition( p90, td, tr, tr, tt) ;
           V(clk180) <+ transition( p180, td, tr, tr, tt) ;
           V(clk270) <+ transition( p270, td, tr, tr, tt) ;

                                                       Best Regards,

                                                          Sheldon
Back to top
 

Picture1_008.png
View Profile   IP Logged
sheldon
Community Fellow
*****
Offline



Posts: 751

Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #6 - May 4th, 2011, 10:22pm
 
newic,

  Part II

  BTW found the clksyn problem.

  If code=0, then the simulation runs. If code is a non-zero value
than the simulation stops. If you look in the simulation log file, you
will see an error message to the effect that "the delay is greater than
the maximum delay of 0", see Geoffrey Coram's comment.

  If you set the maximum delay value for the absdelay function
to be greater than 0, then the simulation will run. Please see the
following code snippet

              maxdelayval = (PI_step/2)*clkperiod ;


              @( cross( V(clksyn) - vcc/2 , dir)) begin
                      c0 = (V(code0) > vcc/2) ? 1:0;
                      c1 = (V(code1) > vcc/2) ? 1:0;
                      c2 = (V(code2) > vcc/2) ? 1:0;
                      c3 = (V(code3) > vcc/2) ? 1:0;

                      validcode = c0 + 2*c1 + 4*c2 + 8*c3 ;
              end

           p0      =      absdelay(V(clkref), validcode*resolution, maxdelayval);
           p90      =      absdelay(V(clkref), validcode*resolution+clkperiod/4, maxdelayval);
           p180      =      absdelay(V(clkref), validcode*resolution+clkperiod/2, maxdelayval);
           p270      =      absdelay(V(clkref), validcode*resolution+3*clkperiod/4, maxdelayval);

So the issue is not the cross function, it is that you defined the
maximum delay as 0. As a result, for any non-zero delay, the
simulation terminates.

                                                       Best Regards,

                                                          Sheldon
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2386
Silicon Valley
Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #7 - May 5th, 2011, 12:10am
 
absdelay() is a big expensive hammer for a very simple job. You should be using the delay in the transition filter rather than absdelay(), which is intended for the more difficult job of delaying analog signal rather than delaying piecewise constant signals.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
newic
Senior Member
****
Offline



Posts: 138

Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #8 - May 5th, 2011, 6:31am
 
thanks for the helpful Smiley

btw, what is the transition filter?
I should use transition function to implement the delay function for a pulse wave signal?
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1999
Massachusetts, USA
Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #9 - May 5th, 2011, 6:32am
 
Ken -
You're absolutely right.  I hope newic invests the time to really understand your comment.  >:(
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2386
Silicon Valley
Re: verilogA,error  when clkref & clksyn arrive at the same time
Reply #10 - May 5th, 2011, 8:24pm
 
transition filter is transition()

-Ken
Back to top
 
 
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.