Dear all,
I have encountered a problem. I want to use a block for 40 times in my verilog-A code. I have written a module for it, but in the main module I can't instantiate it in a "for/generate" loop.
The problem is that the "for/generate" loops should be in the analog block while the instantiating should be outside of the analog block. At least this is the issue that I found. Does anybody have any solution for that?
Kind regards,
Navids

Hi B O E,

Thank you for your suggestion. I had already done that. But I encounter another problem.
In my overall system, I have 8 stages that in each of them I should use 155 times of my child module. If I write the code of the child module directly in the main module with for/generate loops, it works for one stage. but when I tried with three stages, there was this error:

Internal error found in spectre during SpectreHDL complie, during generation of Artist DPLs. Please run 'getSpectreFiles' or send the netlist, the spectre log file, the behavioral model files, and any other information that can help identify the problem to support@cadence.com.
 assertion failed.

I should mention that the child module is not complicated. It two inputs/outputs and according to the control line the inputs are connected to the outputs in parallel/crossed.

Navids