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newic Senior Member Offline Posts: 138	stability & phase margin simulation Jun 06^th, 2011, 7:33pm I try to simulate the stability & phase margin of this simple regulator as a test case. I use the classic method, which large C & L are used to break to feedback path. Is this setup correct? ps: the decap at vout is not shown.
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newic Senior Member Offline Posts: 138	Re: stability & phase margin simulation Reply #1 - Jun 6^th, 2011, 7:34pm I also try out the stb analysis in cadence. The setupp as in the figure. However the result i got is very far different to the case1 which is using large LC.
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: stability & phase margin simulation Reply #2 - Jun 6^th, 2011, 10:21pm hi, in the first setup, where you are applying ac signal? And could you please post both loop gain plots? Because i feel both should give same result at least till UGB. By the way what are values of L and C? Thanks. Raj.
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newic Senior Member Offline Posts: 138	Re: stability & phase margin simulation Reply #3 - Jun 6^th, 2011, 10:31pm ac input set in the schematic Vac=1 at the plus input of the opamp L=1k Henry C=1M farad
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buddypoor Community Fellow Offline Posts: 529 Bremen, Germany	Re: stability & phase margin simulation Reply #4 - Jun 7^th, 2011, 12:00am Hi newic, the stability margin is defined for the loop gain - that means that you must insert the test signal into the loop. That is the reason for including the capacitor of 1F. Therefore, connect the cap not to ground but to the test voltage and dont forget to ac-ground the pos. voltage input node.
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Ken Kundert

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Re: stability & phase margin simulation
Reply #5 - Jun 7^th, 2011, 12:24am

Breaking the loop by inserting an extremely large series inductor and shunt capacitor is not the 'classic approach' to measuring loop gain, it is the method used by people who don't know any better. It is should not be used because it rarely gives accurate results, particularly at frequencies up near the unity gain frequency, where you most need the results to be accurate.

The explanation given by Buddypoor is also important and should be heeded.

-Ken

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newic

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Re: stability & phase margin simulation
Reply #6 - Jun 7^th, 2011, 1:19am

hi all,
thx for the feedback so that i could learn from the forum.
OK, it is not the classic approach but i always heard this method using large LC. Someone also told me that there is no much difference to inject ac signal from plus input of the opamp as shown in case1.

From buddypoor view, i should inject the ac signal in series with the large C right? I called this as case3 over here.

here are the results from case1 & case3.
Now the phase is start from -180o instead of 0o as in normal Bode plot. To overlap it, i minus the phase in case1 with 180o. Will it be stable?

pls give some comments on the differences

what causes the overshoot response in phase_case1?

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phase_and_gain.png

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: stability & phase margin simulation Reply #7 - Jun 7^th, 2011, 2:10am hi ken, i think L and C will give farly accurate result i guess , because for the people who uses Hspice they don't have .stb like in spectrea. @ newic: You should give ac voltage source at the other side of the cap, rather you grounded that side. Thanks.
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newic Senior Member Offline Posts: 138	Re: stability & phase margin simulation Reply #8 - Jun 7^th, 2011, 2:20am Quote: @ newic: You should give ac voltage source at the other side of the cap, rather you grounded that side. the other side (plus input of the opamp) is ac grounded as buddypoor said. why need inject signals both sides?
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buddypoor Community Fellow Offline Posts: 529 Bremen, Germany	Re: stability & phase margin simulation Reply #9 - Jun 7^th, 2011, 5:39am Newic, I think it looks rather good now. The loop gain phase starts at -180 deg which is correct - and at magnitude=0 dB the phase is app. -250 deg. This gives a phase margin of 110 deg. For my opinion, it is even a bit to large. Question: Where did you measure the output signal? It should be at Vout.
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newic Senior Member Offline Posts: 138	Re: stability & phase margin simulation Reply #10 - Jun 7^th, 2011, 6:02am yup, measured at vout. why at high frequency, the phase plot is very different?
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buddypoor

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Re: stability & phase margin simulation
Reply #11 - Jun 7^th, 2011, 6:17am

Not only the phase plots differ. Look at the magnitudes.
The reason is as follows: The "crude" L-C method changes the load conditions at the breaking point (L causes an ac break of the loop).
That was the background of Ken Kundert's doubts.
Correct loop gain simulations don't disconnect the load at this point. �

By the way, for my opinion the magnitude of only 9.6 dB is a rather low value. Therefore, the excessive phase margin. Are you sure, everything else is OK? CHECK the operating point of the opamp!

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newic Senior Member Offline Posts: 138	Re: stability & phase margin simulation Reply #12 - Jun 7^th, 2011, 7:20am yup. the gain is very low and it will cause steady-state error. It is just a test case for breaking the feedback loop study. The phase plot starts at -180o, will it conflict with the bode-plot phase plot & phase margin?
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newic Senior Member Offline Posts: 138	Re: stability & phase margin simulation Reply #13 - Jun 7^th, 2011, 7:23am For stability simulation with feedback path, we got to break the feedback path (unless using stb). How about other ac simulations with feedback path? such as PSR (power supply ratio) plot? I dont think we need to break the loop again. thank you
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buddypoor

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Re: stability & phase margin simulation
Reply #14 - Jun 7^th, 2011, 7:37am

1.) The loop gain phase for low frequencies (including dc) MUST be -180 deg. due to the neg. feedback case. Otherwise the whole circuit would not work.

2.) I don't understand your question regarding PSRR.
Determination of stability margins require breaking the loop - otherwise you cannot inject a test signal. However, in order to restore the operating point, the dc loop must be maintained. Therefore the large L. But this crude method cannot mirror the load at the breraking point.
Other and more exact methods (Middlebrook et al) can do both:
Maintain dc operating point and no loading errors.
Ken Kundert has written a good paper that describes these methods.

Remark: Sorry, it was F. Wiedmann who has collected something about phase margin:

http://sites.google.com/site/frankwiedmann/loopgain

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« Last Edit: Jun 7^th, 2011, 10:36am by buddypoor »

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