How can I get a reset input and reset the D-flip flop in the following code ? Your kind help would be appreciated as I have no knowledge of Verilog

module d_ff(vin_d, vclk, vout_q, vout_qbar);
input vclk, vin_d;
output vout_q, vout_qbar;
electrical vout_q, vout_qbar, vclk, vin_d;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 2.5;
parameter real vtrans = 2.5;
parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);

integer x;

 analog begin
     @ (cross( V(vclk) - vtrans_clk, +1 ))
           x = (V(vin_d) > vtrans);
     V(vout_q) <+ transition( vlogic_high*x +  vlogic_low*!x, tdel, trise, tfall );
     V(vout_qbar) <+ transition( vlogic_high*!x + vlogic_low*x, tdel, trise, tfall );

  end

endmodule

yes i looked at it but i was confused.there are 2 D flip flops on http://www.designers-guide.org/VerilogAMS/ page , one is under the heading of functional models other is RF models. will both work in cadence virtuoso ?
secondly can u kindly also point me to some comprehensive book on Verilog-A?