Hello everyone.

I try to be specific: I'm using the Cadence tools.

- I wrote some Verilog modules for a design (counter, shift registers, etc..)

- Using RTL Compiler I synthesis the design

- I load the desing in Encounter and I do P&R

- Send back the layout to Virtuoso

- Encounter produces a post-P&R verilog netlist

- Import the post-P&R verilog netlist in Virtuoso: this generates the schematic view for all the verilog blocks I wrote for this design

- Run DRC and LVS: during the LVS there is a mistake. One gate (NAND2) is supposed to have input A connected to VDD but Encounter did not make the connection. Ok, I do the connection and LVS is clean.

- Now I want to run AMS-simulations. I setup everything, netlist is ok and compiler is ok, but when I arrive at the Elaboration I receive the following error:

ncelab: *E,CUVNAS (<my_path>/counter_12bit/schematic/verilog.vams,206|19): segmentation of  a signal
.VDD( VDD ), .A( VDD ), .B( reset ) );

Now, this is exactly the port that I connected by hand in Virtuoso and wasn't connected by Encounter (so, I guess there is something related here).

This connection has not been made by me, but it is the result of the synthesized netlist, so I guess that the synthesizer knew what it was doing when it connected the pin A of the NAND2 gate to VDD.

I assume this is some kind of "bug" or something that requires a workaround. I found 2 threads in this forum pointing to the same problem: the first was solved with an update of the tool (I'm already using the last version).

The second thread can be found here http://www.designers-guide.org/Forum/YaBB.pl?num=1249430631 but I have to admit it wasn't really helpful.

Do you have any ideas how to solve this problem?

thanks for the help

Konx