Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Jul 31
st
, 2024, 3:19am
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Simulators
›
Circuit Simulators
› is it possible to write single measurement expression for duty-cycle in hspice?
‹
Previous topic
|
Next topic
›
Pages: 1
is it possible to write single measurement expression for duty-cycle in hspice? (Read 5964 times)
newic
Senior Member
Offline
Posts: 138
is it possible to write single measurement expression for duty-cycle in hspice?
Jan 09
th
, 2012, 11:24pm
is it possible to write single measurement expression for duty-cycle in hspice? so that my mt output files did not contain not important data (assume I have many important expression to measure)
.meas dc_out_a trig v(out) val='0.5*vcc08' rise=4 targ v(out) val='0.5*vcc08' fall=4 $wanna skip this
.meas dc_out_b trig v(out) val='0.5*vcc08' rise=4 targ v(out) val='0.5*vcc08' rise=5 $wanna skip this
.meas dc_out param = '(dc_out_a/ dc_out_b)*100'
Back to top
IP Logged
raja.cedt
Senior Fellow
Offline
Posts: 1516
Germany
Re: is it possible to write single measurement expression for duty-cycle in hspice?
Reply #1 -
Jan 10
th
, 2012, 12:37am
some time back i have used hspice, and i am sure you can find the command in the h spice manual.
Thanks,
Raj.
Back to top
IP Logged
newic
Senior Member
Offline
Posts: 138
Re: is it possible to write single measurement expression for duty-cycle in hspice?
Reply #2 -
Jan 10
th
, 2012, 10:46pm
hspice does not allow multiple equation/function in single expression as like in spectre
any expert?
Back to top
IP Logged
spiceoracle
Junior Member
Offline
Posts: 21
USA
Re: is it possible to write single measurement expression for duty-cycle in hspice?
Reply #3 -
Apr 23
rd
, 2012, 8:56am
No, it is not possible to write one measure statement to measure the duty cycle. You need to measure the period and pulse width using separate measure statements and then calculate the duty cycle using a third measure statement.
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
»» Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.