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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › how to save the output digital data in a file using Verilog-A

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how to save the output digital data in a file using Verilog-A (Read 16004 times)

afridi

Junior Member

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Posts: 24

how to save the output digital data in a file using Verilog-A
Jan 22^nd, 2012, 5:28am

Hi,
I have designed a CT delta-sigma modulator. I want to take the digital output into a text file so that I can process that data in MATLAB. I dont have a complete understanding of Verilog-A in the available cadence virtuoso suite of ver 5.1 . Could anyone share any model or code for this which I can add as a block.

I tried to use the following Spectre-AHDL code also from some reference

node [V, I] in, clk, out;
parameter real thres=1.65;
parameter integer dis_mod=1;
parameter string filename;
{
stream fptr;
integer count;
real inr;
real t=1e-9;
initial
{
fptr = $fopen(filename,"w");
count=0;
}
analog
{
inr = V(in);
if ($threshold( V(clk) - thres, 1 ))
{
$fstrobe(fptr,"%f \n", inr);
count=0;
}
V(out) <- $transition(inr,0,t,t);
}
}

but it shows me the following error

******************
DC Analysis `dcOp'
******************

Internal error found in spectre during DC analysis `dcOp'. �Please run
� � � �`getSpectreFiles' or send the netlist, the spectre log file, the
� � � �behavioral model files, and any other information that can help
� � � �identify the problem to support@cadence.com.
� �"/home/sohaib/SGB25VD/skel/cdb/DSM_blocks/file_dump/ahdl/ahdl.def" 16:
� � � �Segmentation fault.

If someone could explain me this issue that would be helpful as well in solving my problem.

Regards

The more things you do, the more you can do.(Lucille Ball)

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boe

Community Fellow

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Posts: 615

Re: how to save the output digital data in a file using Verilog-A
Reply #1 - Jan 24^th, 2012, 8:58am

Hi dfury,
afridi wrote on Jan 22^nd, 2012, 5:28am:

Hi,
...
but it shows me the following error

******************
DC Analysis `dcOp'
******************

Internal error found in spectre during DC analysis `dcOp'. �Please run
� � � �`getSpectreFiles' or send the netlist, the spectre log file, the
� � � �behavioral model files, and any other information that can help
� � � �identify the problem to support@cadence.com.
� �"/home/sohaib/SGB25VD/skel/cdb/DSM_blocks/file_dump/ahdl/ahdl.def" 16:
� � � �Segmentation fault.

If someone could explain me this issue that would be helpful as well in solving my problem.

Regards

You have encountered a tool BUG. Contact Cadence support.
BTW, which tool versions do you use?

- B O E

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afridi Junior Member Offline Posts: 24	Re: how to save the output digital data in a file using Verilog-A Reply #2 - Jan 24^th, 2012, 9:21am How to find tool version? I am using Cadence Virtuoso 5.14
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: how to save the output digital data in a file using Verilog-A Reply #3 - Jan 24^th, 2012, 11:52am afridi wrote on Jan 24^th, 2012, 9:21am: How to find tool version? Somewhere in the output before the error message, you should see the simulator name and version (Spectre 7.0.1_122, just to make up an example).
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Forum Administrator YaBB Administrator Offline Posts: 145	Re: how to save the output digital data in a file using Verilog-A Reply #4 - Jan 24^th, 2012, 2:54pm Or you can run "spectre -W". -Ken
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afridi Junior Member Offline Posts: 24	Re: how to save the output digital data in a file using Verilog-A Reply #5 - Jan 24^th, 2012, 6:18pm The version is Spectre 5.1.0
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boe Community Fellow Offline Posts: 615	Re: how to save the output digital data in a file using Verilog-A Reply #6 - Jan 25^th, 2012, 3:26am Dfury, afridi wrote on Jan 24^th, 2012, 6:18pm: The version is Spectre 5.1.0 that is an ancient version. I suggest you change to a recent one. - B O E
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afridi Junior Member Offline Posts: 24	Re: how to save the output digital data in a file using Verilog-A Reply #7 - Jan 25^th, 2012, 4:20am ok. You mean to upgrade the whole Cadence suite or just Spectre? Do you think the error is there because this version is old?
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boe Community Fellow Offline Posts: 615	Re: how to save the output digital data in a file using Verilog-A Reply #8 - Jan 25^th, 2012, 7:29am Dfury, Quote: Do you think the error is there because this version is old? Updating spectre should be enough. You should use a MMSIM 10.x or MMSIM 11.x. Knowing Cadence design support, they will tell you to update first anyway; also, this problem is probably already solved. - B O E
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afridi Junior Member Offline Posts: 24	Re: how to save the output digital data in a file using Verilog-A Reply #9 - Jan 25^th, 2012, 7:31am Kindly could you direct me to the solution of my initial problem?
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boe Community Fellow Offline Posts: 615	Re: how to save the output digital data in a file using Verilog-A Reply #10 - Jan 25^th, 2012, 7:36am Dfury, I usually use Verilog-A, not SpectreHDL; but the code seems not too bad to me. However, I would expect the line Code: inr = V(in); directly before the line Code: $fstrobe(fptr,"%f \n", inr); - B O E
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afridi Junior Member Offline Posts: 24	Re: how to save the output digital data in a file using Verilog-A Reply #11 - Jan 26^th, 2012, 5:54am Hmmm, The error is still showing up. I guess there is some problem with its compiler. Can anyone help me translate this into Verilog-A?
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Geoffrey_Coram

Senior Fellow

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Posts: 1999
Massachusetts, USA

Re: how to save the output digital data in a file using Verilog-A
Reply #12 - Jan 27^th, 2012, 6:54am

Code:

`include "disciplines.vams"
module myoutput( in, clk, out);
inout in, clk, out;
electrical in, clk, out;

parameter real thres=1.65;
parameter integer dis_mod=1;
parameter string filename = "default.txt";

integer fptr;
integer count;
real inr;
real t;

analog begin
 �@(initial_step) begin
 � �t=1e-9;
 � �fptr = $fopen(filename,"w");
 � �count=0;
 �end

 �inr = V(in);
 �@(cross( V(clk) - thres, 1)) begin
 � �$fstrobe(fptr,"%f \n", inr);
 � �count=0;
 �end

 �V(out) <+ transition(inr,0,t,t);

 �@(final_step) begin
 � �$fclose(fptr);
 �end
end
endmodule

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: how to save the output digital data in a file using Verilog-A Reply #13 - Jan 27^th, 2012, 6:56am As I was translating, I had a few questions: 1) Why is count always 0? 2) Why is t a variable instead of a parameter?
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afridi Junior Member Offline Posts: 24	Re: how to save the output digital data in a file using Verilog-A Reply #14 - Jan 28^th, 2012, 2:11am hmm I dont know exactly, This code I read from this thesis liu.diva-portal.org/smash/get/diva2:19990/FULLTEXT01
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