Hi,
I have designed a CT delta-sigma modulator. I want to take the digital output into a text file so that I can process that data in MATLAB. I dont have a complete understanding of Verilog-A in the available cadence virtuoso suite of ver 5.1 . Could anyone share any model or code for this which I can add as a block.
I tried to use the following Spectre-AHDL code also from some reference
node [V, I] in, clk, out;
parameter real thres=1.65;
parameter integer dis_mod=1;
parameter string filename;
{
stream fptr;
integer count;
real inr;
real t=1e-9;
initial
{
fptr = $fopen(filename,"w");
count=0;
}
analog
{
inr = V(in);
if ($threshold( V(clk) - thres, 1 ))
{
$fstrobe(fptr,"%f \n", inr);
count=0;
}
V(out) <- $transition(inr,0,t,t);
}
}
but it shows me the following error
******************
DC Analysis `dcOp'
******************
Internal error found in spectre during DC analysis `dcOp'. Please run
`getSpectreFiles' or send the netlist, the spectre log file, the
behavioral model files, and any other information that can help
identify the problem to support@cadence.com.
"/home/sohaib/SGB25VD/skel/cdb/DSM_blocks/file_dump/ahdl/ahdl.def" 16:
Segmentation fault.
If someone could explain me this issue that would be helpful as well in solving my problem.
Regards