Geoffrey_Coram wrote on Jan 27^th, 2012, 6:56am:

As already mentioned, I would expect
Code:

  @(cross( V(clk) - thres, 1)) begin
    inr = V(in);
    $fstrobe(fptr,"%f \n", inr);
    count=0;
  end 

instead of
Code:

  inr = V(in);
  @(cross( V(clk) - thres, 1)) begin
    $fstrobe(fptr,"%f \n", inr);
    count=0;
  end 

Anyway, neither code should cause internal errors on current Spectre versions.
- B O E

Never ever do the following:
Code:

inr = V(in);
V(out) <- $transition(inr,0,t,t); 

In other words, the first argument to the transition function should never be a continuous function of an electrical signal, even if you believe the electrical signal is constant. In contrast, the following is perfectly fine:
Code:

@(cross( V(clk) - thres, 1))
    inr = V(in);
V(out) <- $transition(inr,0,t,t); 

The difference her is that inr is set in an event block and so cannot vary continuously with V(in).

Many times I have seen code that looks like the following:
Code:

if (...)
    val = 1;
else
    val = 0;
V(out) <+ transition(val*V(vdd), 0, 10n);
 

Such code leads to heartbreak and misery. The problem is that V(vdd) is computed by the simulator, and can change slightly from time point to time point (often time these changes are at the attovolt level). Those changes will activate the transition function, which limits the time steps and slow the simulation. You should instead use:
Code:

if (...)
    val = 1;
else
    val = 0;
V(out) <+ V(vdd)*transition(val, 0, 10n);
 

-Ken

boe wrote on Jan 30^th, 2012, 5:27am:


What I understand is,that the inr in the first case would save the its values after the clock voltage crosses over the threshold, but in the second case it will save the value before the clock voltage?

Then is the second approach completely wrong? or their effect is the same?
Regards

"string" was not part of Verilog-AMS in the beginning, but some simulators allowed you to specify a string literal (something in "quotes") -- digital Verilog allowed some conversion between characters and 8-bit "reg" data values.  Since "string" wasn't a keyword, you couldn't use it, but Verilog has some automatic parameter type determination, so you could specify a string literal as the default value and this would effectively make the parameter of type string.

Ah, but in another thread, Afridi admitted to running 5.10 (and was admonished there to get a more recent version).