Hi All,

Actually I need to do behavioral modeling of LDO using Verilog-A. Since I am new to it I thought to get familiar with the process using Cadence SpectreVerilog tool.
so I written a Verilog-A code for a simple INVERTER & tried to simulate. I followed the procedure for the below link

http://www.ee.siue.edu/~jwade/tutorial/cadence_mixed-signal/ams_tutorial.html

I did all the steps in the above tutorial & at the end while I am trying to simulate the schematic I am getting the following error.

"The design does not have any interface nets connecting analog and digital components. Interface elements are needed to synchronize the mixed-signal simulators. you must create at least one interface net in the design inorder to run mixed-signal simulation"


What might be the problem.??
Can anyone help me in this regard??

Hi sri.sagar,

We even don't know your design. Would you please have more details here, like your schematic, verilog-A code for that LDO?

Yawei

Hi, I am sri.sagar's friend & I am doing the actual design.
Thank you all for your replay..

1st In the above Image, I just simulated a small design with 2 inverters coded in VERILOG-A since I am new to it. Now I know the process that how to do with Verilog-A using Cadence Spectre tool.

Hi @geoffrey_Coram, I just followed the procedure in that link (tutorial) & tried to do with a small inverter program. I followed the steps correctly, Now I am able to simulate.

Hi Ywguo, till now I didn't start with the design of LDO.

Hi despap, Yes, you r right I used the "Spectre" as simulator other than "SpectreVerilog"(as shown in that tutorial). & in View Name I have selected "Schematic" So that now I am able to run any of my Verilog-A codes..

Now I am going to start with the Actual Design of LDO. I really don't know how to start coding the Verilog-A for LDO.??
Do I need to write the code according to the circuit?? or only for the Equations of gain. load regulator etc..??

Can anyone Help me in this regard. Thanking you.