Geoffrey_Coram
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The circuit matrix in Spice is flat, so I don't think there would be any difference. You might get something, though, if the elements are ordered differently -- eg, if all the MOS models are placed sequentially in the flat netlist, then you might find the simulation goes faster because the MOS evaluation code is already in the CPU's L1 cache, compared with a hierarchical netlist that has different element types shuffled around. But if it made a large difference, the simulators would sort the elements by type, or they might run all MOS elements on one CPU/thread, and others on a different thread.
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