Hi simulator guru's!

Suppose we compare a flat design versus a hierarchical design. My question is: does the hierarchy influence the simulation run time?

Presumably, netlisting will take longer for the flat one, but what about the actual simulation? To keep the comparison fair, let's assume the same amount of nodes is saved, and that the amount of saved nodes is small. So with respect to simulation run time, is it beneficial to use hierarchy?

The circuit matrix in Spice is flat, so I don't think there would be any difference.  You might get something, though, if the elements are ordered differently -- eg, if all the MOS models are placed sequentially in the flat netlist, then you might find the simulation goes faster because the MOS evaluation code is already in the CPU's L1 cache, compared with a hierarchical netlist that has different element types shuffled around.  But if it made a large difference, the simulators would sort the elements by type, or they might run all MOS elements on one CPU/thread, and others on a different thread.

Are you using Berkeley Spice 3f5?  Or a commercial tool?  Do you know if you have a sparse matrix solver?

I would expect that adding anything to the circuit would make it go slower; voltage sources in particular add matrix rows.  Though I suppose there will be cases where it would go faster.

"Small" circuits are dominated by element evaluation time, and "large" by matrix solution time, but what "small" and "large" are may depend on your simulator, the cache sizes, and the types of elements.