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varun

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CMOS CCII using translinear loop
Apr 04^th, 2012, 11:07am

hello everyone,
i m designing current controlled CMOS second generation current conveyor using translinear loop. I want to perform ac and dc analysis of the circuit . Can anybody tell me how to perform these analysis and how to get the current form the output terminal(z), i m using cadence spectre simulator for the simulation of this circuit at 0.18um technolgy.

i have also attached the circuit in this post

thanking u

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CCII.png

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Geoffrey_Coram

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Re: CMOS CCII using translinear loop
Reply #1 - Apr 5^th, 2012, 2:43pm

Your question is very poorly posed. I can't tell if you have no idea how to run a dc analysis in Spectre (because you're used to Spice3 or HSpice or something), or if you know how to run an analysis but you don't know how to save currents in Spectre, or if you have no idea how to turn the picture into a Spectre netlist.

Do you have a netlist?

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If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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varun

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Re: CMOS CCII using translinear loop
Reply #2 - Apr 7^th, 2012, 2:45am

sir,
i know how to perform the analysis of the circuit but i find it difficult to get the diffrence of current from two series transistor M7 & M6(ie Z+) terminal by applying a current at X terminal.
i want to sweep the current at X terminal and get the same current at Z+terminal.
is it possible to design this circuit at single supply(ie Vdd and gnd)??

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sheldon Community Fellow Offline Posts: 751	Re: CMOS CCII using translinear loop Reply #3 - Apr 9^th, 2012, 5:15am Varun, Is this the testbench you are using? How do you set the dc level at Z+? Best Regards, Sheldon
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achim.graupner Community Member Offline Posts: 51	Re: CMOS CCII using translinear loop Reply #4 - Apr 10^th, 2012, 3:27am Hi one more hint: CMOS translinear loops (exploiting the exponential V-I behavior) are very vulnerable to the mismatch of the threshold voltage (much more than when using bipolar devices). May see my MIXDES'2000 paper "THE SWITCHED TRANSLINEAR PRINCIPLE AND ITS APPLICATION" regards Achim
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varun

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Re: CMOS CCII using translinear loop
Reply #5 - Apr 10^th, 2012, 10:54am

hello sir,
The main problem that i m facing in designing this circuit is how to set the W/L of the transistors constituting translinear loop. I want to put all transistors in saturation region and earlier this circuit was simulated using BJT in which current follows exponential behaviour. So i want to know how to set the w/l values of these transistors while keeping them in saturation.
i m designing this circuit in 0.18um UMC technology with vdd=+0.9v
and VSS=-0.9v with biasing current of 50u.
thanks

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