I'm not sure anyone on this forum can answer your specific questions without violating non-disclosure agreements.  Your best bet would be to contact your foundry representative.

That said, I can give you some starting points based on simple concepts.  One gets correlations of devices when they share processing steps: core NMOS and PMOS will have a correlation from the oxide thickness, but not from their threshold voltage implant.  1V and 3V devices probably have different oxide thicknesses, so they would not be correlated from that.  However, all MOS devices (including mod_var) will likely have correlations from the over/under-etch (delta-W, delta-L).

Beyond that, you'll have to ask the foundry rep, or carefully study the process documents you have: does the vpnp share any processing steps with nmos1v?  Are the n or p implants of one device created the same way as the other?

Since the devices won't share every processing step, though, there won't be perfect correlation for any two device types.  It may be difficult, also, to know how much of the variation in a particular device is due to a processing step that is shared with another, and how much is due to other steps.

easyads,

My experience is very similar to what Kevin has outlined.  Models will show devices tracking over process corners when in real life that is never the case.  You can learn a lot about this by reading the actual model files even though they can seem cryptic at first.  Especially for resistors, many fabs control the variation much more closely than what models predict.  For example, if you simulate +/-20% process variation of a resistor you may see 10% in real life across many wafers.

Since you are at the mercy of the fast/slow corners for process simulation, you can try a process Monte Carlo sim and see if you get different results.

Hope this helps.

Tim