pcardoso73
Junior Member
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Posts: 25
Portugal
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Dear all,
I am very new to Verilog AMS. I would like to do a piece of software for PLLs, so the user could simulate at macro level the basic parameters of a PLL, and thus have an idea of the topology, inversion region, jitter, etc, before going into transistor level.
I would like to divide this into several steps:
1 - A piece of software that could be integrated into Cadence using Spectre RF for PLLs 2 - Create a Library with individual components, so the designer could add them on a schematic view. 3 - Frequency and time domain should be possible to be simulated 4 - Operation in weak, moderate and strong inversion shoul be taken into account, as well as the trade-off jitter/inversion region. 5 - There should be a connection between the macro-model and the design kit used.
As I am quite new to Verilog-Ams, I would like some hints about the flow I should follow, and if the ideas above are feasible.
Best regards, Pedro Cardoso
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