Hello,

I am Hardik Parekh working in the domain of analog & mixed signal modeling & verification..

I have successfully modeled & verified a PLL of VCO frequency 1.6GHz in Verilog-AMS. All the design parameters (charge pump current, loop filter parameters, VCO gain etc.) are parameterized in the model so that model can be used for different PLL frequency with same architecture.

When I use the same model for a different PLL with VCO frequency 3.4GHz (by inserting new design parameters), the PLL doesn't lock & it keeps oscillating around the center frequency which I programmed..

I tried all the simulator options for accuracy (I use Questa-ADMS simulator in which I used EPS value as 1e-06) but am not able to get the desired result..

I ran the actual SPICE simulation of this PLL which gives me correct result for the test case I used for the model.

So, I am not able to figure out whether it is it a modeling issue or a simulator issue..

Any suggestions/directions to investigate further on this topic??