Hi! I am doing a mixed-signal design using a control unit for my analoge part. I wrote it in VHDL in modelsim and then synthesized it using Encounter and AMS C35 library file and checked the post synthesis verilog code in Modelsim and it passed the test bench.

Now I want to use it beside my analoge unit. I created a cell view for it and chose verilog editor and functional as the cell view. Now when running the simulation it gives me an error that the instance in the library with cell view functional is not found?

Could you please help me what I should exactly do to be able to run this verilog generated cell in my analoge design?

Thanks