Below is a version of Sample and Hold Model with External Clock Input That functions in Cadence Virtuoso Transient Simulation properly. I have simulated it with Cadence PSS and PAC, and  the simulator does not complain of any hidden states. However, the PAC simulation result does not generate the sinc function frequency response and instead simply has no out put (zero).

Can someone give me some hints on how to go about debug this??

Thanks
Marduke


`include "disciplines.vams"
`include "constants.vams"


//  Sample & Hold with Extrernal Clock and No Hidden State
//

module SH_NHS_EXCLK (pout, nout,clk,pin, nin);

   input clk, pin, nin;
   output pout, nout;
   electrical clk, pin, nin, pout, nout;

   parameter real clk_thresh =  1/2 from (-inf:inf);
   parameter integer clk_dir =  1 from [-1:+1] exclude 0;
                                   // if dir=+1, rising clock edge triggers
                                   // if dir=-1, falling clock edge triggers
                                                                 
                                     
   parameter real tclkd = 10p from [0:inf);            // output delay (s)
   parameter real trf   = 10p from [0:inf);            // output transition time (s)
   
   real out;
   integer sampleNow;


   analog begin
       
       sampleNow=0;
       
     @(initial_step or cross(V(clk) - clk_thresh, clk_dir))
           sampleNow=1;

       out = idt(0,V(pin,nin),sampleNow);
     
     V(pout,nout) <+ transition( out, tclkd, trf,trf );



   end
   
endmodule

Thank you Frank, that site did help me understand the issue better...