Go,TB
Junior Member
![* *](https://designers-guide.org/forum/Templates/Forum/default/starblue.gif)
Offline
Posts: 11
|
I'm new to Verilog-AMS modeling and need helps to check my code as below.
What the main module means to do is just to delay the clock signal to a D-flip-flop, and then the output of the D-flip-flop is delayed as output of the main module.
//define D flip-flop module adffp (d, clk, q) ...... ...... endmodule
//main ckt module module testx (inx, clk, outx); input inx; voltage inx; input clk; voltage clk; output outx; voltage outx; parameter real vh=1; parameter real vl=0; parameter real td=20n;
electrical clkdd; //internal net electrical outdd; //internal net
analog begin V(clkdd) <+ absdelay(V(clk), 2*td); //delay clk signal by "2*td" adffp dffpx (inx, clkdd, outdd); //instantiation of adffp module with clkdd and inx V(outx) <+ absdelay(V(outdd), 5*td); //delay outdd by "5*td" and then port it out end endmodule[/color]
The simulation is done by HSPICE and it complains that "Syntax error, unsupported syntax or illegal keyword at/before 'dffpx', ..."
I wonder if it's legal to instantiate the module "adffp" inside analog behavior block. Is there better way to implement the function?
Thanks!
|