conr
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Hi Geoffrey, many thanks for your reply. I did a mistake coping the verilog model inside the topic. the real model had also a second section for transitorial analysis:
@ ( initial_step("tran") ) begin halfref = vref / 2; end
@ (cross(V(vclk) - vtrans_clk, 1)) begin unconverted = V(vin); for (i = (`NUM_ADC_BITS-1); i >= 0 ; i = i - 1) begin vd[i] = 0; if (unconverted > halfref) begin vd[i] = vlogic_high; unconverted = unconverted - halfref; end else begin vd[i] = vlogic_low; end unconverted = unconverted * 2; end end
// // assign the outputs // V(vd7) <+ transition( vd[7], tdel, trise, tfall ); V(vd6) <+ transition( vd[6], tdel, trise, tfall ); V(vd5) <+ transition( vd[5], tdel, trise, tfall ); V(vd4) <+ transition( vd[4], tdel, trise, tfall ); V(vd3) <+ transition( vd[3], tdel, trise, tfall ); V(vd2) <+ transition( vd[2], tdel, trise, tfall ); V(vd1) <+ transition( vd[1], tdel, trise, tfall ); V(vd0) <+ transition( vd[0], tdel, trise, tfall );
The problem was the initialization of the variable halfref done just for "tran" simulation. I added "pss" in the initial_step function and now it works also for pss analysis.
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