When simulating a circuit in LTSpice, I would like to see the noise generated on my power bus by fast changes in current draw and then see the noise filtered when I add bypass capacitors. I thought I could do this by adding the ESR, ESL and parasitic capacitance to my ideal voltage source. Once I add ESR for example I do see "noise" on the power bus but adding a bypass capacitor of any value doesn't seem to affect anything. I've attached an image of the circuit that I'm working with. V+ is the power bus. C1 is the bypass capacitor. V2 is the ideal voltage source that I'm trying to make non-ideal, currently ESR=3ohms and I've added L1 to model the supply inductance. The value of C1 is being stepped over in repeated simulations to see its affect on the transient of V+ but there is no appreciable change.