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fgcsk

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current limiter
Nov 20^th, 2012, 12:22am

Hi all,

I just wrote a current limiter. It works but the result is a little bit strange.
Code:

`include "constants.vams"
`include "discipline.vams"

module current_limiter(in,out);
inout in, out;
electrical in, out;
parameter imax = 3e-3;

analog
begin
if(I(in,out) >= imax && V(in,out) >= 0)
 � � � �I(in,out) <+ imax;
else
 � � � �V(in,out) <+ 0;
end
endmodule

Given the input voltage(top fig.) and a series resistor, the current(bottom fig.) limits at 3mA. But I don't know why the current is somewhat distorted before it reaches the limit?

Thanks.

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boe Community Fellow Offline Posts: 615	Re: current limiter Reply #1 - Nov 20^th, 2012, 3:22am fgcsk, Most likely, this is a plotting artefact caused by widely-spaced simulator time points. By the way, your implementation is not recommended. A better implementation can be found at http://www.designers-guide.org/VerilogAMS/ - B O E
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fgcsk

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Re: current limiter
Reply #2 - Nov 20^th, 2012, 7:09am

boe wrote on Nov 20^th, 2012, 3:22am:

fgcsk,

Most likely, this is a plotting artefact caused by widely-spaced simulator time points.

By the way, your implementation is not recommended. A better implementation can be found at http://www.designers-guide.org/VerilogAMS/

- B O E

Above is .tran 1us 32us
Even if I change it to .tran 0.01us 32us, it still have the same problem:

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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: current limiter Reply #3 - Nov 20^th, 2012, 11:19am If you want to resolve the corners you will need to add a cross function. If you have access to my book on Verilog-AMS, I recommend you take a look at sections 6.2 and 6.3 (page 71-73). -Ken
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fgcsk

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Re: current limiter
Reply #4 - Nov 20^th, 2012, 1:03pm

Ken Kundert wrote on Nov 20^th, 2012, 11:19am:

If you want to resolve the corners you will need to add a cross function. If you have access to my book on Verilog-AMS, I recommend you take a look at sections 6.2 and 6.3 (page 71-73).

-Ken

I've tried that. But it doesn't solve the problem. Cry

Actually I think the problem doesn't happen right at corners.

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boe Community Fellow Offline Posts: 615	Re: current limiter Reply #5 - Nov 20^th, 2012, 2:50pm Ken Kundert wrote on Nov 20^th, 2012, 11:19am: If you want to resolve the corners you will need to add a cross function. ... Ken, the model is a limiter, so it should never cross the limit. - B O E
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Ken Kundert

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Re: current limiter
Reply #6 - Nov 20^th, 2012, 5:44pm

Both Boe and I are trying to point you to the answer without having to spend a lot of time trying to explain a somewhat confusing topic. So, you should look at the model that BOE pointed you to (the current limited voltage regulator on the Verilog-AMS page) and if you do not understand it you should read the section of my book that I pointed you to.

-Ken

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« Last Edit: Dec 5^th, 2012, 8:06am by Ken Kundert »

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fgcsk

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Re: current limiter
Reply #7 - Nov 28^th, 2012, 12:07am

I finally solved this problem.
Here's the code:
Code:

`include "disciplines.vams"

module current_limiter(in,out);
inout in, out;
electrical in, out;
parameter imax = 3e-3;

analog
begin
@(cross(I(in,out)+V(in,out)-imax,0))
;
if(I(in,out)+V(in,out) > imax)
	I(in,out) <+ imax;
else
	V(in,out) <+ 0;

end
endmodule

By using a way similar to the diode model(p73, Ken's book), I cut on a diagonal in the IV plane and get the condition: I(in,out)+V(in,out) > imax, then the problem could be solved.

But I still don't know why I should not cut twice as before: I(in,out) >= imax && V(in,out) >= 0. Does it cause convergence problems?

thanks.

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boe

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Re: current limiter
Reply #8 - Nov 28^th, 2012, 2:44am

fgcsk wrote on Nov 28^th, 2012, 12:07am:

...
But I still don't know why I should not cut twice as before: I(in,out) >= imax && V(in,out) >= 0. Does it cause convergence problems?

Yes. If the model is in current limit mode and (e.g. due to rounding errors) the current gets slightly smaller, the original model immediately shorts the terminals whatever the voltage across the limiter.

- B O E

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fgcsk New Member Offline Posts: 7	Re: current limiter Reply #9 - Nov 28^th, 2012, 8:32am boe wrote on Nov 28^th, 2012, 2:44am: Yes. If the model is in current limit mode and (e.g. due to rounding errors) the current gets slightly smaller, the original model immediately shorts the terminals whatever the voltage across the limiter. - B O E Could you illustrate this more detailedly? Didn't get it
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boe

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Re: current limiter
Reply #10 - Dec 5^th, 2012, 4:46am

fgcsk wrote on Nov 28^th, 2012, 8:32am:

...
Could you illustrate this more detailedly?
Didn't get it Huh

I'll try. For example: Suppose you are at V(in,out) = 1 Volt and I(in, out) = imax. Then the model should use the current path. If I(in,out) now changes to imax-ε due to numerical errors, your first model jumps to V(in, out) = 0 creating a discontinuity.

This discontinuity is not only wrong (in this case), but can also cause convergence difficulties.

- B O E

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