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Deadok

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Verilog-A compilation error
Nov 23^rd, 2012, 5:00am

Dear All,

I have a Verilog-A model of a transistor.
I built a super simple test bench in cadence and tried to run a simulation.
Netlist was built successfully, however the error appeared during the compilation phase:

Error found by spectre during AHDL read-in.
� �ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file ***/ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.

In the ahdlcmi.out file I may several lines like this:

Compiling C file InGaAs_NMOS_func.c (optimize) with -O0

***/bin/gcc �-march=k8 -ffast-math -O0 -m64 -DSYSV -DSVR4 -D_REENTRANT -fPIC � -DconfigSPECTRE -I. -I/***/cadence/release2012/mmsim_v11.10.366/tools.lnx86/spectre/ahdlcmi/include -c InGaAs_NMOS_func.c -o obj/optimize/5.0/InGaAs_NMOS_func.o || rm -f -f obj/optimize/5.0/InGaAs_NMOS_func.o

InGaAs_NMOS_func.c: In function 'InGaAs_NMOS_AcLoad':
InGaAs_NMOS_func.c:3603: error: expected expression before ')' token

I put "***" to hide the exact paths as it doesn't change the situation.
What may cause a problem? What would you recommend me to do?

I would appreciate any advice.

Thanks.

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boe

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Re: Verilog-A compilation error
Reply #1 - Nov 24^th, 2012, 11:06am

Deadok,
I think the message is clear enough:
Deadok wrote on Nov 23^rd, 2012, 5:00am:

...
If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.

This is a tool bug. The compiler should never issue messages like this:
Quote:

InGaAs_NMOS_func.c:3603: error: expected expression before ')' token

- B O E

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Verilog-A compilation error Reply #2 - Nov 26^th, 2012, 6:38am It probably is a tool bug, but I suspect only so far as the compiler failed to detect a syntax error in your original Verilog-A code and report that. Where did you get the Verilog-A model from?
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Deadok New Member Offline Posts: 3	Re: Verilog-A compilation error Reply #3 - Nov 29^th, 2012, 6:23am Hello! The problem is still here. I got the model from Stanford: http://nano.stanford.edu/model_iiiv.htm Hope that will help. How would you recommend to check the Verilog-A code? Thanks.
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Verilog-A compilation error Reply #4 - Nov 30^th, 2012, 7:05am Wow, that's really complicated code. If I had to, I'd start commenting out sections of the code and see if I could narrow down the problem. Eg, you could comment out the gate leakage stuff. I've never seen a model with so many for loops!
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