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TB ground issue? (Read 1687 times)
RolfK
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TB ground issue?
Dec 07th, 2012, 2:21pm
 
Dear All,
below my first TB. Simulation with spectre is OK. But the result is very questionalble.
I have likely a ref gnd issue. I tried to define the gnd (ref node 0) like shon in Ken Kunderts book. But this leads to error messages at compile time.
Also I would appriciate if someone coild comment on this first trial. I just wnt to emulate a power up sequence.
Thanks a lot

########### code #########################
`include "constants.vams"
`include "disciplines.vams"

module tb_digital_core ;  

// tb vars
electrical  vdd_io ;
electrical  vdd_core ;
electrical      common_gnd ;
// "ground common_gnd" or also  "ground gnd" lead to erro message


analog begin
      @(initial_step) begin
           V(vdd_io) <+ 0 ;
           V(vdd_core) <+ 0 ;
           V(common_gnd) <+ 0 ;
     end

     V(vdd_io)      <+  transition(3.3,5n,10m) ;      
     V(vdd_core) <+  transition(1.25,10n,20m) ;      

end

// DUT Instanciation
digital_core dut (                                              
     .vdd_reg_in      (vdd_io) ,  
     .vdd_core              (vdd_core) ,  
     .common_gnd     (common_gnd)                                              
) ;                                            

endmodule      
################# end ######################
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Ken Kundert
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Silicon Valley
Re: TB ground issue?
Reply #1 - Dec 7th, 2012, 10:25pm
 
Verilog-A does not support node numbers, so you cannot use 0 to represent ground (I try to make that clear in my book).


You can declare a node to be ground using:
Code:
electrical gnd;
ground gnd; 



If you do that, you cannot also add the following:
Code:
analog V(gnd) <+ 0; 

That would create a loop of shorts.

Now, lets think about a simplified version of what you proposed.
Code:
analog begin
     @(initial_step)
	    V(vdd) <+ 0 ;

     V(vdd) <+  transition(1.25,10n,20m);
end 


The initial_step triggers on the first timepoint, meaning that on the first time point, this code simplifies to:
Code:
analog begin
	V(vdd) <+ 0 ;
	V(vdd) <+ transition(1.25,10n,20m);
end 


The contribution operators sum all contributions made at the same time point, so this is equivalent to:
Code:
analog begin
	V(vdd) <+ 0 + transition(1.25,10n,20m);
end 


Thus, the initial_step block does not do any thing.

Finally, the transition filter only operates upon changes in its arguments. In this example, the argument never changes, so the transition filter can be removed without changing the behavior. In the final simplification, the above is equivalent to:
Code:
analog begin
	V(vdd) <+ 1.25;
end 


So, I would not expect your supplies to ramp up like you want.

Perhaps you can try something like the following:
Code:
real Vdd;
analog begin
     @(timer(10n))
	    Vdd = 3.3;

     V(vdd) <+  transition(Vdd,0,20m);
end 



One more thing. You should never put a contribution statement in an event block. Fortunately, when you did it you contributed zero, which really doesn't do anything. If you have used a non-zero value you would have driven the circuit with impulses, which is always problematic.

-Ken
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« Last Edit: Dec 8th, 2012, 9:11am by Ken Kundert »  
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