Hi,

I am trying to run simulations on a mixed-signal design using Verilog-A block behaviour modelling. But when I try to netlist, I get the following error:
"Netlisting failed as function hnlNetNameOnTerm was called on currect instance ... in design ... Ensure that argument to this function is a valid terminal name and netlist again."

My design contains 2 instances on same multi-bit registers (I6 & I7) and this error message is shown after each time I netlist after modifying the Verilog-A code. I also have one more Register (I12) instantiated which is also a Verilog-A block but has different bit width. They all have different inputs.
I am not using any `define statements in these instances that may cause problems. the other flipflop (I12) of different width on modifying and netlisting again doesn't show this error but then my original flipflop instances (I6 and I7) now behave as having same bit-width as the I12.
They have same terminal names but different bit-widths. Isn't it okay to use "D<1:N>" as terminal name for all registers? I mean many blocks have same names like "clk" on them. Shouldn't thatt cause same conflicts too, in case that my current problem is on similar lines.

Thanks

-Nikhil

My module is defined this way:
{
`include "constants.vams"
`include "disciplines.vams"
`define N 20  //Number of D Flipflops in this register array

module DFF_Array_20bits(q, qb, clk, d);
output [N:1] q, qb;
electrical [N:1] q, qb;

input [N:1] d;
electrical [N:1] d;

input clk; electrical clk;
...
....
...
...

endmodule
}

Now, I instantiate 3 such modules in my schematic. Two of them have 20 bit-width and the third one having bit-width of 6. But soon I realised that the `define was global and was taking the smallest value i.e. 6 from the 3rd Flipflop instance. So I replaced N everywhere with the number of bits and I was now left with 2 separate modules. One with bit-width of 20 and another with bit-width of 6 with no global `define to mess around.

Now, I instantiate 2 flipflop arrays with 20 bit-width each (same module twice) since I need a total of 40 bit-width and the other module (with different terminal and part names) for 6 bit-width. I could have changed the bit-width inside the module to 40 directly, but I wanted to know the reason for this happening so that I can figure out if the like happens in the future.

Here is my take on the issue: The 2 modules of bit-width 20 each have same terminal names (d<20:1> and q<20:1>) but have different wires connected at the input.
The function called 'hnlNetNameOnTerm' mentioned in the netlisting error is said to do the following: "Returns the signal name of the net attached to the given bit of the terminal of the given name on the current instance being expanded. This function guarantees the same name is returned even if the net is aliased, and this function is later called with a terminal attached to one of the aliases of this net"

I think the 2 instances of same module might be causing the problem. Both have input terminal name as (d<20:1>) where as the wires attached to them are P<20:1> and P<40:21> respectively. But don't many instances have same terminal names? like 'clk' and other such common names? What seems to be the real problem and how do I fix it?

-Nikhil