rajdeep
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Sorry for my ignorance. What is PSP? Google says Penn State Philips models. Can we simulate such models using Cadence Spectre?
Also, assuming I will not get any PSP model for our devices, is it possible to model the effect of charge injection for worst case scenario i.e. let all the charge be injected on to the node that affects the design most. For example, I have a scenario where a PMOS (5u/500n) switch turns off, and I suspect that the charge injection can lift the drain of the PMOS, and this can cause some issue in the design as the net connected to the drain of the PMOS is a critical net. To model the adversity that charge injection may cause I have added an extra cap (like 100fF) between the gate and drain of the PMOS. But I understand this could be an overkill. But I blv I can create a pessimistic model for worst case charge injection very crudely by adding such coupling capacitor. Is this a practical method designers (e.g. sw-cap ckt designers) can adopt?
Many thanks for the reply. Rajdeep
Thanks, Rajdeep
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