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Single line assignment to multiple variable (Read 3950 times)

Tobben24 New Member Offline Posts: 2	Single line assignment to multiple variable Mar 19^th, 2013, 4:38am Hi, Is it possible to do single line assignment to multiple variables? Something like this: real one,two,three; one,two,three = 0;
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Geoffrey_Coram

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Posts: 1999
Massachusetts, USA

Re: Single line assignment to multiple variable
Reply #1 - Mar 20^th, 2013, 6:24am

I don't believe the syntax allows
one,two,three = 0;

I believe the lastest (digital) Verilog supports initialization as part of the declaration:
real one=0,two=0,three=0;

and I've found some simulators support new digital features in the AMS context.

Of course, if you just want to do it on one line, you could do
one=0; two=0; three=0;
The statements don't have to be on separate lines.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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Tobben24 New Member Offline Posts: 2	Re: Single line assignment to multiple variable Reply #2 - Mar 20^th, 2013, 7:09am Okay, thanks for the reply:)
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Paul Floyd

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Re: Single line assignment to multiple variable
Reply #3 - Mar 20^th, 2013, 9:44am

Tobben24 wrote on Mar 19^th, 2013, 4:38am:

Hi,

Is it possible to do single line assignment to multiple variables? Something like this:

real one,two,three;
one,two,three = 0;

Variables should be default initialized to zero, so in this case your assignment does nothing. If you want a different value, that's another matter.

If it were allowed, I'd want to follow C++ syntax, where it would be

a = b = c = 0;

A+
Paul

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