oner
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Hey, I m a beginner in Veriloga and new in this Forum. I am trying to build an amplifier. My Problem is that the gain of the Amplifier is dependent on the load resistance. I tried to set the output voltage (V(out) <+1) for getting the output current (r_load = V(out)/I(out)), but this gives me an error : "No DC convergence."
Can you give me an idea to solve this problem ?
Regards
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