Hello spinfab,
Quote:
Yes: $bound_step.

- B O E

Why don't you leave time step control to the simulator? It should be much better at it than you could be. You should limit your self to just informing the simulator of things that it cannot know. There are only a few situations where you really need to give involved in time step selection. They are:

1. If your module is producing a high frequency signal, particularly sine waves, without having a high frequency. Here you need to use $bound_step to inform the simulator of the Nyquist rate for the signal. Typically telling the simulator to take 3-10 points per cycle is sufficient.
2. If your module produces a signal that changes abruptly, like a pulse, or if the module behavior changes abruptly, such as with switches. In this case you generally use an event (@(timer(...)) or @(cross(...))) to force the simulator to place a time point at the time of the abrupt change.
3. If you module is sensitive to a threshold crossing. In this case you would use and @(cross(...)) to accurately resolve the threshold crossing.

That is basically it. If you are not in one of the above situations, you should not be trying to control the time point selection from within Verilog-A. Instead, if you do not feel like you are getting accurate enough results you should tighten reltol. Many people try to control accuracy of a simulation by setting maxstep, but that is a very poor approach.

-Ken