Hi all,

I have started doing some work in Verilog-AMS recently. I have used some of the codes available in the designers guide website for modelling different circuits.

I have also used the code for Ideal OP-AMP available in the site and it has worked perfectly for me. But I am having a little trouble in the understanding of the code (means how it works)...!!


I am quoting the code:::



// Ideal Opamp
//
// Version 1a, 1 June 04
//
// Ken Kundert
//
// Downloaded from The Designer's Guide Community (www.designers-guide.org).
// Post any questions on www.designers-guide.org/Forum.
// Taken from "The Designer's Guide to Verilog-AMS" by Kundert & Zinke.
// Chapter 5, Listing 1.

`include "disciplines.vams"

module ideal_opamp (pout, nout, pin, nin);
   output pout, nout;
   input pin, nin;
   electrical pin, nin, pout, nout;
   
   branch (pout,nout) out;
   branch (pin,nin) in;

   analog begin
     V(out): V(in) == 0;
   end
endmodule



I am unable to understand what the branch command does??

and also what does " V(out): V(in) == 0 "  mean??

Anyone having the answer pls help.

Thanks in advance,

Indrajit

The branch statement simply declares a branch. It creates the branch and gives it a name.

The magic is in the "V(out): V(in) == 0;". You can read this statement as: Find V(out) such that V(in) == 0. This is just a rather direct statement of the virtual short circuit principle. V(in), meaning the voltage between pin and nin, is forced to be 0, but notice that nothing is contributing to or driving the in branch, and so no current flows from pin to nin.

-Ken