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Verilog-A compiler directive question (Read 2031 times)
danmc
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Verilog-A compiler directive question
Jul 24th, 2013, 9:28am
 
Is there a way to check multiple macros with an `ifdef?  What I would like is:

`define CASE1
// `define CASE2
// `define CASE3

// what I want to do next is
`if defined(CASE1) || defined(CASE2)
// do something
`endif


obviously the defined() bit isn't valid, but is there some easy way of doing this?  I suppose I could do:
`ifdef CASE1
`define CASE1_OR_2
`endif

`ifdef CASE2
`define CASE1_OR_2
`endif

`ifdef CASE1_OR_2
//do stuff
`endif

but that seems like an ugly solution.  Is there a nicer way?

Thanks
-Dan
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Geoffrey_Coram
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Massachusetts, USA
Re: Verilog-A compiler directive question
Reply #1 - Aug 2nd, 2013, 8:45am
 
I don't see anything in the LRM that would help; looks like you're stuck with the ugly solution.
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